plan view of the MPEG-Encoder
The encoder is based on the Fujitsu MPEG-2 System MB86391. This is a special developed DSP for real time video compression. Bases on this SR-Systems has developed an encoder board for D-ATV application which incorporates the necessary peripheral components like SDRAMs, audio- and video-Codecs as well as all required power supply demands (3,3 and 1,8 V).
The encoder supports the formats SIF (352×288 Pixel), HD1 (352×576 Pixel) and D1 (720×576 Pixel) at data rates from 0,5 Mbit/s to 15 Mbit/s. This data rate includes already a 20-bit-stereo audio channel. The encoder firmware can individually be adjusted and is launched during system start.
Data out supplies a transportstream (SPI) according to ISO/IEC 13818 to an 8 bit TS-Interface with clock and Frame sync signal.
Video inputs are selectable between CVBS and Y/C (S-Video). Optional there is a parallel-input according to ITU-656 available.
Download for the MPEG-Encoder |
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MPEG-Encoder-V4_Desc-en_075dpi.pdf, 191,143 Bytes Connector- and pin descriptionConnector description of the MPEG-Encoder V4, including pin description. 2 pages DIN A4, 75 dpi |
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MPEG-Encoder-V3_Desc-en_075dpi.pdf, 180,643 Bytes Connector- and pin descriptionConnector description of the MPEG-Encoder V3, including pin description. 2 pages DIN A4, 75 dpi Obsolete! This product isn't available any longer!In order to be complete, we decided to leave the connector description sheet on this site. |
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